SH7720 Datasheet, PDF (837/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 USB Host Controller (USBH)
Initial
Bit
Bit Name Value R/W Description
4
UE
0
R/W Unrecoverable Error
This bit is set when the host controller detects a system
error that is not related to USB. HCD clears this bit after
the host controller is reset.
0: System error is not generated
1: System error is detected
3
RD
0
R/W Resume Detected
This bit is set when the host controller detects that a
device of USB issues a resume signal. This bit is not set
when HCD sets USB Resume state.
0: The resume signal is not detected
1: The resume signal is detected
2
SF
0
R/W Start of Frame
This bit is set by the host controller when each frame
starts and after the Hcca Frame Number is updated. The
host controller simultaneously generates the SOF token.
0: Each frame has not initiated or Hcca Frame Number is
not updated
1: Initiation of each frame and updating of Hcca Frame
Number
1
WDH
0
R/W Write-back Done Head
This bit is set immediately after the host controller has
written Hc Done Head to Hcca Done Head. Hcca Done
Head is not updated until this bit is cleared. HCD should
clear this bit only after the content of Hcca Done Head has
been stored.
0: When cleared after set to 1
1: When Hc Done Head is written to Hcca Done head
0
SO
0
R/W Scheduling Overrun
This bit is set when the USB schedule has overrun after
Hcca Frame Number has updated. SchedulingOverrun
also increments the SOC bit in USBHCS.
0: The USB schedule has not overrun
1: The USB schedule has overrun
Rev. 3.00 Jan. 18, 2008 Page 775 of 1458
REJ09B0033-0300