SH7720 Datasheet, PDF (1403/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 38 Electrical Characteristics
CKIO
A23 to A0
A12/A11*¹
CSn
RD/WR
RAS
CAS
DQMx
D15 to D0
BS
CKE
DACKn*²
Td1
Td2
Td3
Td4
Td5
Td6
Td7
Td8
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tde
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
Column Column Column Column Column Column Column
Address1 Address2 Address3 Address4 Address5 Address6 Address7
tAD1
tCSD1
READ
Command
Column
Address8
tAD1
tAD1
tAD1
tCSD1
tRWD1
tRASD1
tCASD1
tDQMD1
tBSD
tRWD1
tRASD1
tCASD1
tCASD1
tDQMD1
tRDS2
tRDS2
tRDS2
tRDS2
tRDS2
tRDS2
tRDS2
tRDS2
tRDH2
tRDH2
tRDH2
tRDH2
tRDH2
tRDH2
tBSD
tRDH2
tRDH2
tDACD
(High)
tDACD
Notes: 1. Address pin that is connected to A10 of SDRAM
2. Waveform when active low is specified for DACKn
Figure 38.29 Burst Read Bus Cycle of SDRAM (Single Read × 8)
(Bank Active Mode: READ Command,
Same Row Address, CAS Latency 2, TRCD = 1 Cycle)
Rev. 3.00 Jan. 18, 2008 Page 1341 of 1458
REJ09B0033-0300