SH7720 Datasheet, PDF (752/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
21.3.4 Receive Data Register (SIRDR)
SIRDR is a 32-bit read-only register that reads receive data of the SIOF. SIRDR stores data in the
receive FIFO and is initialized by the conditions specified in section 37, List of Registers, or by a
receive reset caused by the RXRST bit in SICTR.
Initial
Bit
Bit Name Value R/W Description
31 to 16 SIRDL All 0
R
15 to 0
Left-Channel Receive Data
Store data received from the SIOFRxD pin as left-
channel data. The position of the left-channel data in
the receive frame is specified by the RDLA bit in
SIRDAR.
• These bits are valid only when the RDLE bit in
SIRDAR is set to 1.
15 to 0 SIRDR All 0
R
15 to 0
Right-Channel Receive Data
Store data received from the SIOFRxD pin as right-
channel data. The position of the right-channel data in
the receive frame is specified by the RDRA bit in
SIRDAR.
• These bits are valid only when the RDRE bit in
SIRDAR is set to 1.
Rev. 3.00 Jan. 18, 2008 Page 690 of 1458
REJ09B0033-0300