SH7720 Datasheet, PDF (681/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
Figure 18.4 shows an example of the operation for transmission in asynchronous mode.
1
Serial
data
TDFE
Start
bit
0 D₀
Parity Stop Start
Data bit bit bit
D₁
D₇ 0/1 1 0 D₀
Parity Stop
Data bit bit 1
D₁
D₇ 0/1 1
Idle
state
(mark state)
TEND
Transmit-FIFO-
Data written to
Transmit-FIFO-
data-empty
SCFTDR and TDFE
data-empty
interrupt request flag read as 1 then interrupt request
cleared to 0 by Transmit-
FIFO-data-empty
interrupt handler
One frame
Figure 18.4 Example of Transmit Operation
(Example with 8-Bit Data, Parity, One Stop Bit)
• Transmit data stop function
When the value of the SCTDSR register and the number of transmit data match, transmit
operation stops. Setting the TSIE bit (interrupt enable bit) allows the generation of an interrupt
and activation of DMAC.
Figure 18.5 shows an example of the operation for transmit data stop function.
Transmit data
TxD
Start
bit
0 D0 D1
Parity Stop
bit bit
D6 D7 0/1
Start
bit
0 D0 D1
D6 D7 0/1
TSF flag
Figure 18.5 Example of Transmit Data Stop Function
Rev. 3.00 Jan. 18, 2008 Page 619 of 1458
REJ09B0033-0300