SH7720 Datasheet, PDF (140/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Instruction Code
Fx: 0000
Fx: 0001
Fx: 0010
Fx: 0011 to 1111
MSB
LSB MD: 00
MD: 01
MD: 10
MD: 11
0010 Rn Rm 11MD CMP/STR Rm, Rn
XTRCT Rm, Rn
MULU.W Rm, Rn
MULSW Rm, Rn
0011 Rn Rm 00MD CMP/EQ Rm, Rn
CMP/HS Rm, Rn
CMP/GE Rm, Rn
0011 Rn Rm 01MD DIV1 Rm, Rn
DMULU.L Rm,Rn
CMP/HI Rm, Rn
CMP/GT Rm, Rn
0011 Rn Rm 10MD SUB
Rm, Rn
SUBC Rm, Rn
SUBV Rm, Rn
0011 Rn Rm 11MD ADD
Rm, Rn
DMULS.L Rm,Rn
ADDC
Rm, Rn
ADDV Rm, Rn
0100 Rn Fx
0000 SHLL Rn
DT
Rn
SHAL
Rn
0100 Rn Fx
0001 SHLR Rn
CMP/PZ Rn
SHAR
Rn
0100 Rn Fx
0010 STS.L MACH, @–Rn STS.L MACL, @–Rn STS.L
PR, @–Rn
0100 Rn 00MD 0011 STC.L SR, @–Rn
STC.L GBR, @–Rn STC.L
VBR, @–Rn STC.L SSR, @–Rn
0100 Rn 01MD 0011 STC.L SPC, @–Rn
0100 Rn
10MD 0011 STC.L
R0_BANK, @–Rn
STC.L
R1_BANK, @–Rn
STC.L
R2_BANK, @–Rn
STC.L
R3_BANK, @–Rn
0100 Rn
11MD 0011 STC.L
R4_BANK, @–Rn
STC.L
R5_BANK, @–Rn
STC.L
R6_BANK, @–Rn
STC.L
R7_BANK, @–Rn
0100 Rn Fx
0100 ROTL Rn
ROTCL Rn
0100 Rn Fx
0101 ROTR Rn
CMP/PL Rn
ROTCR Rn
0100 Rm Fx
0110 LDS.L
@Rm+, MACH
LDS.L @Rm+, MACL LDS.L
@Rm+, PR
0100 Rm 00MD 0111 LDC.L @Rm+, SR
LDC.L @Rm+, GBR LDC.L
@Rm+, VBR LDC.L @Rm+, SSR
0100 Rm 01MD 0111 LDC.L @Rm+, SPC
0100 Rm
10MD 0111 LDC.L
@Rm+, R0_BANK
LDC.L
@Rm+, R1_BANK
LDC.L
@Rm+, R2_BANK
LDC.L
@Rm+, R3_BANK
0100 Rm
11MD 0111 LDC.L
@Rm+, R4_BANK
LDC.L
@Rm+, R5_BANK
LDC.L
@Rm+, R6_BANK
LDC.L
@Rm+, R7_BANK
0100 Rn Fx
1000 SHLL2 Rn
SHLL8 Rn
SHLL16 Rn
0100 Rn Fx
1001 SHLR2 Rn
SHLR8 Rn
SHLR16 Rn
0100 Rm Fx
1010 LDS
Rm, MACH
LDS
Rm, MACL
LDS
Rm, PR
0100 Rm/ Fx
Rn
1011 JSR
@Rm
TAS.B @Rn
JMP
@Rm
0100 Rn Rm 1100 SHAD Rm, Rn
0100 Rn Rm 1101 SHLD Rm, Rn
Rev. 3.00 Jan. 18, 2008 Page 78 of 1458
REJ09B0033-0300