SH7720 Datasheet, PDF (315/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
8.3.5 Interrupt Request Register 1 (IRR1)
IRR1 is an 8-bit register that indicates whether interrupt requests from the DMAC are generated.
This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in
standby mode.
Bit
7 to 4
Bit Name

3
DEI3R
2
DEI2R
1
DEI1R
0
DEI0R
Initial Value R/W
All 0
R
0
R/W
0
R/W
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
DEI3 Interrupt Request
Indicates whether the DEI3 (DMAC) interrupt is
generated.
0: DEI3 interrupt request is not generated
1: DEI3 interrupt request is generated
DEI2 Interrupt Request
Indicates whether the DEI2 (DMAC) interrupt
request is generated.
0: DEI2 interrupt request is not generated
1: DEI2 interrupt request is generated
DEI1 Interrupt Request
Indicates whether the DEI1 (DMAC) interrupt
request is generated.
0: DEI1 interrupt request is not generated
1: DEI1 interrupt request is generated
DEI0 Interrupt Request
Indicates whether the DEI0 (DMAC) interrupt
request is generated.
0: DEI0 interrupt request is not generated
1: DEI0 interrupt request is generated
Rev. 3.00 Jan. 18, 2008 Page 253 of 1458
REJ09B0033-0300