SH7720 Datasheet, PDF (948/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 26 LCD Controller (LCDC)
26.3.16 LCDC Interrupt Control Register (LDINTR)
LDINTR specifies where to control the Vsync interrupt of the LCD module. See also 26.3.20,
LCDC user specified interrupt control register (LDUINTR) and 26.3.21, LCDC user specified
interrupt line number register (LDUINTLNR) for interrupts. Note that operations by this register
setting and LCDC user specified interrupt control register (LDUINTR) setting are independent.
Bit
Bit Name Initial Value R/W Description
15
MINTEN 0
R/W Memory Access Interrupt Enable
Enables or disables an interrupt generation at the
start point of each vertical retrace line period for
VRAM access by LCDC.
0: Disables an interrupt generation at the start point
of each vertical retrace line period for VRAM
access
1: Enables an interrupt generation at the start point
of each vertical retrace line period for VRAM
access
14
FINTEN 0
R/W Frame End Interrupt Enable
Enables or disables the generation of an interrupt
after the last pixel of a frame is output to LDC panel.
0: Disables an interrupt generation when the last
pixel of the frame is output
1: Enables an interrupt generation when the last
pixel of the frame is output
13
VSINTEN 0
R/W Vsync Starting Point Interrupt Enable
Enables or disables the generation of an interrupt at
the start point of LCDC's Vsync.
0: Interrupt at the start point of the Vsyncl is disabled
1: Interrupt at the start point of the Vsync is enabled
12
VEINTEN 0
R/W Vsync Ending Point Interrupt Enable
Enables or disables the generation of an interrupt at
the end point of LCDC's Vsync.
0: Interrupt at the end point of the Vsync signal is
disabled
1: Interrupt at the end point of the Vsync signal is
enabled
Rev. 3.00 Jan. 18, 2008 Page 886 of 1458
REJ09B0033-0300