SH7720 Datasheet, PDF (360/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
Initial
Bit Bit Name Value R/W Description
10
BSZ1
1*
R/W Data Bus Width
9
BSZ0
1*
R/W Specify the data bus width of spaces.
00: Reserved (setting prohibited)
01: 8-bit size
10: 16-bit size
8 to 0 
All 0 R
11: 32-bit size
Notes: 1. The data bus width for area 0 is specified by the
external pin. The BSZ1 and BSZ0 bit settings in
CS0BCR are ignored.
2. If area 5 or area 6 is specified as PCMCIA space,
the bus width can be specified as either 8 bits or
16 bits.
3. If area 2 or area 3 is specified as SDRAM space,
the bus width can be specified as either 16 bits or
32 bits.
Reserved
These bits are always read as 0. The write value should
always be 0.
Note: * CS0BCR samples the external pins (MD3 and MD4) that specify the bus width at
power-on reset.
Rev. 3.00 Jan. 18, 2008 Page 298 of 1458
REJ09B0033-0300