SH7720 Datasheet, PDF (946/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 26 LCD Controller (LCDC)
26.3.14 LCDC Vertical Sync Signal Register (LDVSYNR)
LDVSYNR specifies the vertical (scan direction and vertical direction) sync signal timing of the
LCD module.
Bit Bit Name
Initial Value R/W Description
15
VSYNW3
0
R/W Vertical Sync Signal Width
14
VSYNW2
0
13
VSYNW1
0
12
VSYNW0
0
R/W Set the width of the vertical sync signals (FLM and
R/W ^{Vsync) (unit: line).}
R/W ^{Specify to the value of (the vertical sync signal}
width) -1.
Example: For a vertical sync signal width of 1 line.
VSYNW = (1-1) = 0 = H'0
11

0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
10
VSYNP10
0
R/W Vertical Sync Signal Output Position
9
VSYNP9
0
8
VSYNP8
1
7
VSYNP7
1
6
VSYNP6
1
5
VSYNP5
0
4
VSYNP4
1
3
VSYNP3
1
2
VSYNP2
1
1
VSYNP1
1
0
VSYNP0
1
R/W Set the output position of the vertical sync signals
R/W ^{(FLM and Vsync) (unit: line).}
R/W ^{Specify to the value of (the number of vertical sync}
signal output position) -2.
R/W
DSTN should be set to an odd number value. It is
R/W _{handled as (setting value+1)/2.}
R/W _{Example: For an 480-line LCD module and a}
R/W ^{vertical retrace period of 0 lines (in other words,}
R/W ^{VTLN=479 and the vertical sync signal is active for}
the first line):
R/W
• Single display
R/W
VSYNP = [(1-1)+VTLN]mod(VTLN+1)
= [(1-1)+479]mod(479+1)
= 479mod480 = 479 =H'1DF
• Dual displays
VSYNP = [(1-1)×2+VTLN]mod(VTLN+1)
= [(1-1)×2+479]mod(479+1)
= 479mod480 = 479 =H'1DF
Rev. 3.00 Jan. 18, 2008 Page 884 of 1458
REJ09B0033-0300