SH7720 Datasheet, PDF (1282/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 36 User Debugging Interface (H-UDI)
36.3 Register Descriptions
The H-UDI has the following registers. Refer to section 37, List of Registers, for more details on
the addresses and states of these registers in each operating mode.
• Bypass register (SDBPR)
• Instruction register (SDIR)
• Boundary scan register (SDBSR)
• ID register (SDID)
• Shift register
36.3.1 Bypass Register (SDBPR)
SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to the bypass
mode, SDBPR is connected between H-UDI pins TDI and TDO. The initial value is undefined.
36.3.2 Instruction Register (SDIR)
SDIR is a 16-bit read-only register. The register is in JTAG IDCODE in its initial state. It is
initialized by TRST assertion or in the TAP test-logic-reset state, and can be written to by the H-
UDI irrespective of the CPU mode. Operation is not guaranteed if a reserved command is set in
this register.
Initial
Bit
Bit Name Value R/W Description
15 to 13 TI7 to TI5 All 1
R
Test Instruction 7 to 0
12
TI4
0
R
11 to 8 TI3 to TI0 All 1
R
The H-UDI instruction is transferred to SDIR by a serial
input from TDI.
For commands, see table 36.2.
7 to 2 
All 1
R
Reserved
These bits are always read as 1.
1

0
R
Reserved
This bit is always read as 0.
0

1
R
Reserved
This bit is always read as 1.
Rev. 3.00 Jan. 18, 2008 Page 1220 of 1458
REJ09B0033-0300