SH7720 Datasheet, PDF (649/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
Figure 18.1 shows the block diagram of SCIF.
Module data bus
RxD
SCK
TxD
SCFRDR (64 stages)
SCRSR
SCFTDR (64 stages)
SCTSR
Parity generation
Parity check
SCFDR
SCFCR
SCFER
SCSSR
SCSCR
SCSMR
SCTDSR
SCBRR
Transmission/
reception control
Baud rate
generator
Clock
External clock
CTS
RTS
[Legend]
SCRSR: Receive shift register
SCFRDR: Receive FIFO data register
SCTSR: Transmit shift register
SCFTDR: Transmit FIFO data register
SCSMR: Serial mode register
SCSCR: Serial control register
SCIF
SCFER: FIFO error count register
SCSSR: Serial status register
SCBRR: Bit rate register
SCFCR: FIFO control register
SCFDR: FIFO data count register
SCTDSR: Transmit data stop register
Figure 18.1 Block Diagram of SCIF
Pφ
Pφ/4
Pφ/16
Pφ/64
SCIF
interrupt
Rev. 3.00 Jan. 18, 2008 Page 587 of 1458
REJ09B0033-0300