SH7720 Datasheet, PDF (1166/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
[1]
[2]
No
Is FRDYI interrupt is generated
or does DMA transfer end?
Yes
Write 1 to DATEN
Does DMA transfer ^No
end?
Yes
Set DMACR to H'00
No
Is DTI interrupt
generated?
Yes
CRCERI or WRERI
Yes
interrupt generated?
No
Yes
Is DTERI interrupt
generated?
No
No
Is DRPI interrupt
generated?
Yes
Is DTBUSY
No
detected?
Yes
No
Is DBSYI interrupt
generated?
Yes
No
TBNCR = n(DRPI)?
Yes
No
Is BTI interrupt
generated?
Yes
Write 1 to CMDOFF
Write 1 to CMDOFF
Write 1 to CMDOFF
Execute CMD12
Set DMACR to H'00
FIFO clear
Note: * n (DRPI): The number of DRPIs from
the start of write sequence
Command sequence end
Figure 31.30 Operational Flowchart for Write Sequence
(Pre-defined Multiblock Transfer) (2)
Rev. 3.00 Jan. 18, 2008 Page 1104 of 1458
REJ09B0033-0300