SH7720 Datasheet, PDF (955/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 26 LCD Controller (LCDC)
Bit Bit Name
Initial Value R/W Description
3 to 1 
All 0
R
Reserved.
These bits are always read as 0. The write value
should always be 0.
0
DON
0
R/W Display On
Specifies the start and stop of the LCDC display
operation.
The control sequence state can be checked by
referencing the LPS[1:0] of LDPMMR.
0: Display-off mode: LCDC is stopped
1: Display-on mode: LCDC operates
Notes: 1. Write H'0011 to LDCNTR when starting display and H'0000 when completing display.
Data other than H'0011 and H'0000 must not be written to.
2. Setting bit DON2 to 1 makes the contents of the palette RAM undefined. Before writing
to the palette RAM, set bit DON2 to 1.
26.3.20 LCDC User Specified Interrupt Control Register (LDUINTR)
LDUINTR sets whether the user specified interrupt is generated, and indicates its processing state.
This interrupt is generated at the time when image data which is set by the line number register
(LDUINTLNR) in LCDC is read from VRAM.
This LCDC issues the interrupts (LCDCI): user specified interrupt by this register, memory access
interrupt by the LCDC interrupt control register (LDINTR), and OR of Vsync interrupt output.
This register and LCDC interrupt control register (LDINTR) settings affect the interrupt operation
independently.
Bit Bit Name
15 to 9 
8
UINTEN
Initial Value R/W
All 0
R
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
User Specified Interrupt Enable
Sets whether generate an LCDC user specified
interrupt.
0: LCDC user specified interrupt is not generated
1: LCDC user specified interrupt is generated
Rev. 3.00 Jan. 18, 2008 Page 893 of 1458
REJ09B0033-0300