SH7720 Datasheet, PDF (314/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
8.3.4 Interrupt Request Register 0 (IRR0)
IRR0 is an 8-bit register that indicates interrupt requests from the TMU and IRQ0 to IRQ5.
Initial
Bit
Bit Name Value R/W Description
7

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
TMU_
0
SUNIR
R/W TMU_SUNI Interrupt Request
Indicates whether the TMU_SUNI (TMU) interrupt request
is generated.
0: TMU_SUNI interrupt request is not generated
1: TMU_SUNI interrupt request is generated
5
IRQ5R 0
R/W IRQn Interrupt Request
4
IRQ4R 0
3
IRQ3R 0
2
IRQ2R 0
1
IRQ1R 0
0
IRQ0R 0
R/W Indicates whether there is interrupt request input to the
R/W ^{IRQn pin. When edge-detection mode is set for IRQn, an}
interrupt request is cleared by writing 0 to the IRQnR bit
R/W _{after reading IRQnR = 1.}
R/W ^{When level-detection mode is set for IRQn, these bits}
R/W
indicate whether an interrupt request is input. The
interrupt request is set/cleared by only 1/0 input to the
IRQn pin.
IRQnR
0: No interrupt request input to IRQn pin
1: Interrupt request input to IRQn pin
[Legend] n = 0 to 5
Rev. 3.00 Jan. 18, 2008 Page 252 of 1458
REJ09B0033-0300