SH7720 Datasheet, PDF (669/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
18.3.9 Bit Rate Register (SCBRR)
SCBRR is an eight-bit readable/writable register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
Bit Bit Name Initial value R/W
7 to 0 SCBRD7 to H'FF
R/W
SCBRD0
Description
Bit Rate Set
The SCBRR setting is calculated as follows:
Asynchronous Mode:
1. When sampling rate is 1/16
N=
Pφ
× 10⁶ - 1
32 × 2^2n-1 × B
2. When sampling rate is 1/5
N=
Pφ
× 10⁶ - 1
10 × 2^2n-1 × B
3. When sampling rate is 1/11
Pφ
N=
× 10⁶ - 1
22 × 2^2n-1 × B
4. When sampling rate is 1/13
N=
Pφ
× 10⁶ - 1
26 × 2^2n-1 × B
5. When sampling rate is 1/27
N=
Pφ
× 10⁶ - 1
54 × 2^2n-1 × B
Synchronous Mode:
N=
Pφ
4 × 2^2n-1 × B
× 10⁶ - 1
Rev. 3.00 Jan. 18, 2008 Page 607 of 1458
REJ09B0033-0300