SH7720 Datasheet, PDF (625/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Realtime Clock (RTC)
17.3.1 64-Hz Counter (R64CNT)
R64CNT indicates the state of the divider circuit between 64 Hz and 1 Hz.
Reading this register, when carry from 128-Hz divider stage is generated, sets the CF bit in the
RTC control register 1 (RCR1) to 1 so that the carrying and reading 64 Hz counter are performed
at the same time is indicated. In this case, the R64CNT should be read again after writing 0 to the
CF bit in RCR1 since the read value is not valid.
After the RESET bit or ADJ bit in the RTC control register 2 (RCR2) is set to 1, the RTC divider
circuit is initialized and R64CNT is initialized to H'00.
R64CNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit
Bit Name Initial Value R/W Description
7

0
R
Reserved
This bit is always read as 0. Writing has no effect.
6
1 Hz
Undefined R
Indicate the state of the divider circuit between
5
2 Hz
Undefined R
64 Hz and 1 Hz.
4
4 Hz
Undefined R
3
8 Hz
Undefined R
2
16 Hz
Undefined R
1
32 Hz
Undefined R
0
64 Hz
Undefined R
Rev. 3.00 Jan. 18, 2008 Page 563 of 1458
REJ09B0033-0300