SH7720 Datasheet, PDF (891/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Bit Bit Name
2
ALTV2
1
ALTV1
0
ALTV0
Section 25 USB Function Controller (USBF)
Initial Value R/W Description
0
R Alternate Value
0
R The alternate setting value is stored when the Set
0
R ^{interface command has been received.}
ALTV is updated when the SETI bit in the interrupt
flag register is set to 1.
25.3.35 Time Stamp Register (TSRH/TSRL)
TSR is a register to store the current time stamp value. The time stamp is updated when the SOF
bit in IFR0 is set to 1. The value of the time stamp when the SOF mark function is enabled and the
SOF packet is broken remains as previous one.
Bit
Bit Name Initial Value R/W
15 to 11 
All 0
R
Description
Reserved.
This bit is always read as 0.
10
D10
0
R Time Stamp Data
9
D9
0
R
8
D8
0
R
7
D7
0
R
6
D6
0
R
5
D5
0
R
4
D4
0
R
3
D3
0
R
2
D2
0
R
1
D1
0
R
0
D0
0
R
Note:
The time stamp register is used as a 16-bit register which consists of upper byte TSRH and
lower TSRL in USBF. TSRH can be read directly, but TSRL is read via an 8-bit temporary
register. Therefore, the registers should be accessed in the order, TSRH and TSRL, in byte
units. TSRL cannot be read singly.
Rev. 3.00 Jan. 18, 2008 Page 829 of 1458
REJ09B0033-0300