SH7720 Datasheet, PDF (1107/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
31.3.12 Card Status Register (CSTR)
CSTR indicates the MMCIF status during command sequence execution.
Initial
Bit
Bit Name Value R/W Description
7
BUSY 0
R
Command Busy
Indicates command execution state. When the CMDOFF bit
in OPCR is set to 1, this bit is cleared to 0 because the
MMCIF command sequence is aborted.
0: Idle state waiting for a command, or data busy state
1: Command sequence execution in progress
6
FIFO_ 0
R
FIFO Full
FULL
When read data is received, this bit is set to 1 after FIFO has
been full. This bit is cleared to 0 when RD_CONTI is set to 1
or command sequence is ended.
0: The FIFO is empty
1: The FIFO is full
5
FIFO_ 0
R
FIFO Empty
EMPTY
When write data is transmitted, this bit is set to 1 after FIFO
has been empty. This bit is cleared to 0 when DATAEN is
set to 1 or command sequence is ended.
0: The FIFO includes data
1: The FIFO is empty
4
CWRE 0
R
Command Register Write Enable
Indicates whether the CMDR command is being transmitted
or has been transmitted.
0: The CMDR command has been transmitted, or the
START bit in CMDSTRT has not been set yet, so the new
command can be written.
1: The CMDR command is waiting for transmission or is
being transmitted. If the new command is written, a
malfunction will result.
Rev. 3.00 Jan. 18, 2008 Page 1045 of 1458
REJ09B0033-0300