SH7720 Datasheet, PDF (1165/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
Command sequence start
FIFO clear
Write transfer block size to TBCR
Execute CMD16
No
Does CMD16 end
successfully?
Yes
Write the number of transfer blocks to TBNCR
Execute CMD23
No
Does CMD23 end
successfully?
Yes
Execute CMD25 (CMDR to CMDSTRT)
Is CRCERI interrupt
Yes
generated?
No
Is CRPI interrupt
No
generated?
Yes
Read response register
Is response status
No
normal?
Yes
Set DMAC
Set DMACR (MMCIF)
No
Is CTERI interrupt
generated?
Yes
[1]
[2]
Figure 31.30 Operational Flowchart for Write Sequence
(Pre-defined Multiblock Transfer) (1)
Rev. 3.00 Jan. 18, 2008 Page 1103 of 1458
REJ09B0033-0300