SH7720 Datasheet, PDF (651/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
18.3 Register Descriptions
SCIF has the following registers. Refer to section 37, List of Registers, for more details on the
addresses and states of these registers in each operating mode. Note that the channel number of
each register is omitted.
(1) Channel 0
• Receive shift register_0 (SCRSR_0)
• Receive FIFO data register_0 (SCFRDR_0)
• Transmit shift register_0 (SCTSR_0)
• Transmit FIFO data register_0 (SCFTDR_0)
• Serial mode register_0 (SCSMR_0)
• Serial control register_0 (SCSCR_0)
• FIFO error count register_0 (SCFER_0)
• Serial status register_0 (SCSSR_0)
• Bit rate register_0 (SCBRR_0)
• FIFO control register_0 (SCFCR_0)
• FIFO data count register_0 (SCFDR_0)
• Transmit data stop register_0 (SCTDSR_0)
(2) Channel 1
• Receive shift register_1 (SCRSR_1)
• Receive FIFO data register_1 (SCFRDR_1)
• Transmit shift register_1 (SCTSR_1)
• Transmit FIFO data register_1 (SCFTDR_1)
• Serial mode register_1 (SCSMR_1)
• Serial control register_1 (SCSCR_1)
• FIFO error count register_1 (SCFER_1)
• Serial status register_1 (SCSSR_1)
• Bit rate register_1 (SCBRR_1)
• FIFO control register_1 (SCFCR_1)
• FIFO data count register_1 (SCFDR_1)
• Transmit data stop register_1 (SCTDSR_1)
Rev. 3.00 Jan. 18, 2008 Page 589 of 1458
REJ09B0033-0300