SH7720 Datasheet, PDF (69/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 1 Overview
Item
Features
SIM card
interface (SIM)
• Single channel ready for ISO7816-3 data protocol (T = 0, T = 1)
• Asynchronous half-duplex character transmission protocol
• Data length of 8 bits
• Generates and checks a parity bit
• Number of output clocks per 1 etu selectable
• Direct convention/inverse convention selectable
• Internal prescaler for Pφ
• Clock polarity changeable at idle time (low or high)
• With interrupt request and DMAC request
MultiMedia Card • Complies with The MultiMedia Card System Specification Version 3.1
interface
(MMCIF)
• Supports MMC mode
• 16.5-Mbps bit rate (max) for the card interface (Pφ = 33 MHz)
• Incorporates sixty-four 16-bit data-transfer FIFOs
• Interrupt and DMA request
• Module standby function
SD host interface •
(SDHI)
Note: Only for
models with the
SDHI
•
Supports SDHC (SD High Capacity) and SDIO
 Supports Part 1 Physical Layer Ver.1.01 to 2.0 of SD Specification, but
not supported for High-Speed
 Supports Part E1 SDIO Ver. 1.00 to 2.00 of SD Specification
SD memory/IO card interface (1 bit/4 bits SD bus)
• SD clock frequency ≤ 1/2 peripheral clock frequency
• Error check function: CRC7 (command/response), CRC16 (data)
• MMC (MultiMedia Card) access
• Interrupt request and DAMC transfer request (SD_BUF read/write)
• Card detection function
• Write protect
SSL accelerator • RSA encryption
(SSL)
• Supported operations: addition, subtraction, multiplication, power operation
Note: SH7720
group only
• DES and Triple-DES encryption/decryption
Rev. 3.00 Jan. 18, 2008 Page 7 of 1458
REJ09B0033-0300