SH7720 Datasheet, PDF (500/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Direct Memory Access Controller (DMAC)
Figure 10.8 shows an example of DMA transfer timing in single address mode.
CKIO
A25 to A0
CSn
WE
D31 to D0
DACKn
Address output to external memory space
Select signal to external memory space
Write strobe signal to external memory space
Data output from external device with DACK
DACK signal (active-low) to external device with DACK
(a) External device with DACK → external memory space (ordinary memory)
CKIO
A25 to A0
CSn
RD
Address output to external memory space
Select signal to external memory space
Read strobe signal to external memory space
D31 to D0
DACKn
Data output from external memory space
DACK signal (active-low) to external device with DACK
(b) External memory space (ordinary memory) → external device with DACK
Figure 10.8 Example of DMA Transfer Timing in Single Address Mode
Rev. 3.00 Jan. 18, 2008 Page 438 of 1458
REJ09B0033-0300