SH7720 Datasheet, PDF (1116/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
31.3.16 VDD/Open-Drain Control Register (VDCNT)
VDCNT can use MMC_ODMOD signal to control open drain. The MMC_VDDON signal output
can be used to control the MMC power supply (VDD) on/off.
Initial
Bit
Bit Name Value R/W
7
VDDON 0
R/W
6
ODMOD 0
R/W
5 to 0 
All 0

Description
Specifies MMC_VDDON signal to be used as a MMC
power supply (VDD) control signal.
0: MMC_VDDON is low signal output
1: MMC_VDDON is high signal output
Specifies MMC_ODMOD signal to be used to control
CMD output open drain in MMC mode.
0: MMC_ODMOD signal is low signal output
1: MMC_ODMOD signal is high signal output
Reserved
These bits are always read as 0. The write value should
always be 0.
31.3.17 Data Register (DR)
DR is a register for reading/writing FIFO data.
Word/byte access is enabled to addresses of this register.
Initial
Bit
Bit Name Value R/W
15 to 0 DR
(7 to 0)
Undefined R/W
Description
Register for reading/writing FIFO data.
Word/byte access is enabled. However, byte access is
disabled to address 2n+1.
Rev. 3.00 Jan. 18, 2008 Page 1054 of 1458
REJ09B0033-0300