SH7720 Datasheet, PDF (378/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
(3) SDRAM
• CS2WCR
Initial
Bit
Bit Name Value R/W Description
31 to 9 
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
8
A2CL1 1
R/W CAS Latency for Area 2
7
A2CL0 0
R/W Specify the CAS latency for area 2.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
6 to 0 
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
• CS3WCR
Initial
Bit
Bit Name Value R/W Description
31 to 15 
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
14
TRP1 0
R/W Number of Cycles from Auto-Precharge/PRE Command to
13
TRP0 0
R/W ^{ACTV Command}
Specify the number of minimum cycles from the start of auto-
precharge or issuing of PRE command to the issuing of
ACTV command for the same bank. The setting for areas 2
and 3 is common.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
12

0
R Reserved
This bit is always read as 0. The write value should always be
0.
Rev. 3.00 Jan. 18, 2008 Page 316 of 1458
REJ09B0033-0300