SH7720 Datasheet, PDF (1475/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
20.3.5 I²C Bus Status Register
(ICSR)
20.7 Usage Notes
Section 21 Serial I/O with FIFO
(SIOF)
21.1 Features
21.2 Input/Output Pins
Table 21.1 Pin Configuration
21.3 Register Descriptions
Page Revision (See Manual for Details)
656 Changed
Bit Bit Name Description
3 STOP Stop Condition Detection Flag
[Setting conditions]
• In master mode: when a stop
condition is detected after frame
transfer is completed
• In slave mode: when a stop
condition is detected after the
address set in SAR matches the
salve address that comes as the
first byte after the detection of a
start condition
[Clearing condition]
• When 0 is written in STOP after
reading STOP = 1
677 Changed
The falling edge of the ninth clock is recognized by
checking the SCLO bit in the I²C bus control register 2
(ICCR2).
679 Deleted
This LSI includes a clock-synchronized serial I/O
module with FIFO (SIOF) that comprises two channels.
The SIOF can perform serial communication with a
serial peripheral interface bus (SPI).
679 SPI mode deleted.
681 All descriptions related to SPI mode deleted.
682 SPI Control Register (SPICR) deleted.
Rev. 3.00 Jan. 18, 2008 Page 1413 of 1458
REJ09B0033-0300