SH7720 Datasheet, PDF (362/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W
10
WR3
1
R/W
9
WR2
0
R/W
8
WR1
1
R/W
7
WR0
0
R/W
6
WM
0
R/W
5 to 2 
All 0 R
Description
Number of Access Wait Cycles
Specify the number of wait cycles that are necessary for
read or write access.
0000: 0 cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (Setting prohibited)
1110: Reserved (Setting prohibited)
1111: Reserved (Setting prohibited)
External Wait Mask Specification
Specifies whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 300 of 1458
REJ09B0033-0300