SH7720 Datasheet, PDF (428/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
(6) Single Write
A write access ends in one cycle when data is written in non-cacheable region and the data bus
width is larger than or equal to access size.
Figure 9.18 shows the single write basic timing.
CKIO
A25 to A0
A12/A11*¹
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*²
Tr
Tc1 Trwl
Tap
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.18 Basic Timing for Single Write (Auto-Precharge)
Rev. 3.00 Jan. 18, 2008 Page 366 of 1458
REJ09B0033-0300