SH7720 Datasheet, PDF (1422/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 38 Electrical Characteristics
38.4.12 I²C Bus Interface Timing
Table 38.14 I²C Bus Interface Timing
Conditions: V_CCQ = 2.7 to 3.6 V, V_CCQ1 = 2.7 to 3.6 V, V_CC = 1.4 to 1.6 V, Ta = –20 to 75°C
Value
Item
Symbol Test Conditions Min.
Typ. Max. Unit Figure
SCL input cycle time
t
SCL
12
t
Pcyc
+
600
  ns 38.52
SCL input high pulse width
t_SCLH
SCL input low pulse width
t
SCLL
SCL, SDA input fall time
t
Sf
SCL, SDA input spike pulse t
SP
removal time
3 t_Pcyc + 300 
5
t
Pcyc
+
300





 ns
 ns
300 ns
1 t ns
cyc
SDA input bus free time
t_BUF
Start condition input hold time t
STAH
Retransmission start condition t_STAS
input setup time
5 t_Pcyc
3t
Pcyc
3 t_Pcyc
  ns
  ns
  ns
Stop condition input setup time t_STOS
Data input setup time
t
SDAS
Data input hold time
t
SDAH
Capacitive load of SCL, SDA Cb
3 t_Pcyc

1
t
Pcyc
+
20

0

0

 ns
 ns
 ns
400 pF
SCL, SDA output fall time
t
Sf
VccQ = 3.0 V 

 250 ns
 300 ns
Note: * t_Pcyc is a cycle time of a peripheral clock (Pφ).
Rev. 3.00 Jan. 18, 2008 Page 1360 of 1458
REJ09B0033-0300