SH7720 Datasheet, PDF (710/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 20 I²C Bus Interface (IIC)
20.2 Input/Output Pins
Table 20.1 summarizes the input/output pins used by the I²C bus interface.
Table 20.1 I²C Bus Interface Pins
Name
IIC clock
IIC data I/O
Pin Name
IIC_SCL
IIC_SDA
Abbreviation I/O
SCL
I/O
SDA
I/O
Function
IIC serial clock input/output
IIC serial data input/output
20.3 Register Descriptions
The I²C bus interface has the following registers:
• I²C bus control register 1 (ICCR1)
• I²C bus control register 2 (ICCR2)
• I²C bus mode register (ICMR)
• I²C bus interrupt enable register (ICIER)
• I²C bus status register (ICSR)
• Slave address register (SAR)
• I²C bus transmit data register (ICDRT)
• I²C bus receive data register (ICDRR)
• I²C bus shift register (ICDRS)
• I²C bus master transfer clock select register (ICCKS)
Rev. 3.00 Jan. 18, 2008 Page 648 of 1458
REJ09B0033-0300