SH7720 Datasheet, PDF (121/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Addressing
Mode
Instruction
Format
Effective Address Calculation Method
Calculation Formula
Immediate
#imm:8
8-bit immediate data imm of TST, AND, OR, or

XOR instruction is zero-extended.
#imm:8
8-bit immediate data imm of MOV, ADD, or

CMP/EQ instruction is sign-extended.
#imm:8
8-bit immediate data imm of TRAPA instruction is 
zero-extended and multiplied by 4.
Note:
For addressing modes with displacement (disp) as shown below, the assembler description
in this manual indicates the value before it is scaled (x1, x2, or x4) according to the operand
size to clarify the LSI operation. For details on assembler description, refer to the
description rules in each assembler.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, GBR)
; GBR indirect with displacement
@ (disp:8, PC) ; PC relative with displacement
disp:8, disp:12 ; PC relative
Rev. 3.00 Jan. 18, 2008 Page 59 of 1458
REJ09B0033-0300