SH7720 Datasheet, PDF (50/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Figure 38.32 Burst Write Bus Cycle of SDRAM (Single Write × 8)
(Bank Active Mode: ACTV + WRIT Command, TRCD = 1 Cycle) .................. 1344
Figure 38.33 Burst Write Bus Cycle of SDRAM (Single Write × 8)
(Bank Active Mode: PRE + ACTV + WRIT Command, TRCD = 1 Cycle)....... 1345
Figure 38.34 Auto Refresh Timing of SDRAM (TRP = 2 Cycles) .......................................... 1346
Figure 38.35 Self Refresh Timing of SDRAM (TRP = 2 Cycles) ............................................ 1347
Figure 38.36 Power-On Sequence of SDRAM (Mode Write Timing, TRP = 2 Cycles).......... 1348
Figure 38.37 Write to Read Bus Cycle in Power-Down Mode of SDRAM
(Auto Precharge Mode, TRCD = 1 Cycle, TRP = 1 Cycle, TRWL = 1 Cycle)... 1349
Figure 38.38 Read to Write Bus Cycle in Power-Down Mode of SDRAM
(Auto Precharge Mode, TRCD = 1 Cycle, TRP = 1 Cycle, TRWL = 1 Cycle)... 1350
Figure 38.39 PCMCIA Memory Card Interface Bus Timing ................................................... 1351
Figure 38.40 PCMCIA Memory Card Interface Bus Timing
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait 1,
Hardware Wait 1) ................................................................................................ 1352
Figure 38.41 PCMCIA I/O Card Interface Bus Timing............................................................ 1353
Figure 38.42 PCMCIA I/O Card Interface Bus Timing
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait 1,
Hardware Wait 1) ................................................................................................ 1354
Figure 38.43 REFOUT, IRQOUT Delay Time ........................................................................ 1354
Figure 38.44 I/O Port Timing ................................................................................................... 1355
Figure 38.45 DREQ Input Timing (DREQ Low Level is Detected) ........................................ 1355
Figure 38.46 DACK Output Timing......................................................................................... 1355
Figure 38.47 TPU Output Timing ............................................................................................. 1356
Figure 38.48 TPU Clock Input Timing..................................................................................... 1356
Figure 38.49 Oscillation Settling Time when RTC Crystal Oscillator is Turned On ............... 1357
Figure 38.50 SCK Input Clock Timing .................................................................................... 1358
Figure 38.51 SCIF Input/Output Timing in Synchronous Mode .............................................. 1359
Figure 38.52 I²C Bus Interface Input/Output Timing ............................................................... 1361
Figure 38.53 SIOF_MCLK Input Timing................................................................................. 1362
Figure 38.54 SIOF Transmission/Reception Timing (Master Mode 1, Fall Sampling)............ 1363
Figure 38.55 SIOF Transmission/Reception Timing (Master Mode 1, Rise Sampling)........... 1363
Figure 38.56 SIOF Transmission/Reception Timing (Master Mode 2, Fall Sampling)............ 1364
Figure 38.57 SIOF Transmission/Reception Timing (Master Mode 2, Rise Sampling)........... 1364
Figure 38.58 SIOF Transmission/Reception Timing (Slave Mode 1, Slave Mode 2) .............. 1365
Figure 38.59 AFEIF Module AC Timing ................................................................................. 1366
Figure 38.60 USB Clock Timing.............................................................................................. 1367
Figure 38.61 LCDC Module Signal Timing ............................................................................. 1369
Figure 38.62 SIM Module Signal Timing ................................................................................ 1370
Figure 38.63 MMCIF Transmit Timing ................................................................................... 1371
Rev. 3.00 Jan. 18, 2008 Page l of lxii