SH7720 Datasheet, PDF (346/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
Name
I/O
WE3(BE3)/DQMUU/ O
ICIOWR
WE2(BE2)/DQMUL/ O
ICIORD
WE1(BE1)/DQMLU/ O
WE
WE0(BE0)/DQMLL O
RAS
O
CAS
O
CKE
O
IOIS16
I
WAIT
I
BREQ
I
BACK
O
MD5 to MD3
I
REFOUT
O
Function
Indicates that D31 to D24 are being written to.
Connected to the byte select signal when a byte-selection SRAM
is connected.
Corresponds to signals D31 to D24 when SDRAM is connected.
Functions as the I/O write strobe signal when the PCMCIA is
used.
Indicates that D23 to D16 are being written to.
Connected to the byte select signal when a byte-selection SRAM
is connected.
Corresponds to signals D23 to D16 when the SDRAM is used.
Functions as the I/O read strobe signal when the PCMCIA is used.
Indicates that D15 to D8 are being written to.
Connected to the byte select signal when a byte-selection SRAM
is connected.
Corresponds to signals D15 to D8 when the SDRAM is used.
Functions as the memory write strobe signal when the PCMCIA is
used.
Indicates that D7 to D0 are being written to.
Connected to the byte select signal when a byte-selection SRAM
is connected.
Corresponds to select signals D7 to D0 when the SDRAM is used.
Connects to RAS pin when SDRAM is connected.
Connects to CAS pin when SDRAM is connected.
Connects to CKE pin when SDRAM is connected.
PCMCIA 16-bit I/O signal
Valid only in little endian mode.
Pulled low in bit endian mode.
External wait input (sampled at the falling edge of CKIO)
Bus request input
Bus acknowledge output
MD5: Selects data alignment (big endian or little endian)
MD4 and MD3: Specify area 0 bus width (8/16/32 bits)
Bus mastership request signal for refreshing
Rev. 3.00 Jan. 18, 2008 Page 284 of 1458
REJ09B0033-0300