SH7720 Datasheet, PDF (840/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 USB Host Controller (USBH)
Bit
Bit Name
29 to 7 
6
RHSC
5
FNO
4
UE
3
RD
2
SF
1
WDH
0
SO
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
0
R/W Root Hub Status Change Enable
0: Ignored
1: Interrupt generation due to RootHubStatusChange
disabled
0
R/W Frame Number Overflow Enable
0: Ignored
1: Interrupt generation due to FrameNumberOverflow
disabled
0
R/W Unrecoverable Error Enable
0: Ignored
1: Interrupt generation due to UnrecoverableError disabled
0
R/W Resume Detected Enable
0: Ignored
1: Interrupt generation due to ResumeDetected disabled
0
R/W Start of Frame Enable (SF)
0: Ignored
1: Interrupt generation due to StartofFrame disabled
0
R/W Write-back Done Head Enable (WDH)
0: Ignored
1: Interrupt generation due to WritebackDoneHead
disabled
0
R/W Scheduling Overrun Enable (SO)
0: Ignored
1: Interrupt generation due to SchedulingOverrun disabled
Rev. 3.00 Jan. 18, 2008 Page 778 of 1458
REJ09B0033-0300