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SH7720 Datasheet, PDF (336/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Section 8 Interrupt Controller (INTC)
Interrupt Source
Priority
Interrupt Interrupt Priority IPR
within IPR Default
Code *1 (Initial Value)
(Bit Numbers) Setting Unit Priority
TMU0 TUNI0
H'400*2 0 to 15 (0)
IPRA

(15 to 12)
High
TMU1 TUNI1
H'420*2 0 to 15 (0)
IPRA (11 to 8) 
TMU2 TUNI2
H'440*2 0 to 15 (0)
IPRA (7 to 4) 
RTC ATI
H'480*2 0 to 15 (0)
IPRA (3 to 0) High
PRI
H'4A0*2
CUI
H'4C0*2
Low
SIM ERI
H'4E0*2 0 to 15 (0)
IPRB (7 to 4) High
RXI
H'500*2
TXI
H'520*2
TEND
H'540*2
Low
WDT ITI
H'560*2 0 to 15 (0)
IPRB (15 to 
12)
REF RCMI
H'580*2 0 to 15 (0)
IPRB (11 to 8) 
Low
Notes: 1. INTEVT2 code.
2. The code set in INTEVT is as same as INTEVT2.
3. The code set in INTEVT indicates interrupt level H'200 to H'3C0. For the
correspondence of interrupt level and INTEVT, see table 8.5.
Rev. 3.00 Jan. 18, 2008 Page 274 of 1458
REJ09B0033-0300