SH7720 Datasheet, PDF (694/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
Start of reception
Set receive trigger number in RTRG1
and RTRG0 in SCFCR
1
Set RFRST bit in SCFCR to 1
2
Clear RFRST bit in SCFCR to 0
Wait
3
1-bit interval elapsed?
No
Yes
Set RE bit in SCSCR
When using receive FIFO data interrupt, 4
set RIE bit to 1
1. Set the receive trigger number
in SCFCR.
2. Reset the receive FIFO.
3. Wait for one bit interval.
4. Reception is started when the RE
bit in SCSCR is set to 1.
5. Read receive data while the RDF
bit is 1.
6. After the end of reception, clear the
RE bit to 0.
RDF =1?
No
Yes
Read receive trigger number of receive
data bytes from SCFRDR
5
Clear RE bit in SCSCR to 0
6
End of reception
Figure 18.15 Sample Serial Reception Flowchart (2)
(Second and Subsequent Reception)
Rev. 3.00 Jan. 18, 2008 Page 632 of 1458
REJ09B0033-0300