SH7720 Datasheet, PDF (1499/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
34.1.22 Pin Select Register D
(PSELD)
Page Revision (See Manual for Details)
1176, Amended
1177 _{Bit Bit Name Description}
14 PSELD14 MMC_DAT/SIOF1_TxD/SD_DAT0/TPU_
13 ^{PSELD13 TI3A Select as PTU2 Other Functions}
00: Select SIOF1_TxD
01: Select TPU_TI3A
10: Select MMC_DAT
11: Select according to PSELB0 setting
Reserved when PSELB0 = 0
Select SD_DAT0 when PSELB0 = 1
10 PSELD10 SIOF1_MCLK/SD_DAT1/TPU_TI3B
9 ^{PSELD9 Select as PTU3 Other Functions}
00: Select SIOF1_MCLK
01: Select TPU_TI3B
10: Reserved
11: Select according to PSELB0 setting
Reserved when PSELB0 = 0
Select SD_DAT1 when PSELB0 = 1
6 PSELD6 SIOF1_SYNC/SD_DAT2 Select as PTU4
5 ^{PSELD5 Other Functions}
00: Select SIOF1_SYNC
01: Reserved
10: Reserved
11: Select according to PSELB0 setting
Reserved when PSELB0 = 0
Select SD_DAT2 when PSELB0 = 1
2 PSELD2 SIM_CLK/SCIF1_SCK/SD_DAT3 Select
1 ^{PSELD1 as PTV0 Other Functions}
00: Select SCIF1_SCK
01: Reserved
10: Select SIM_CLK
11: Select according to PSELB0 setting
Reserved when PSELB0 = 0
Select SD_DAT3 when PSELB0 = 1
Rev. 3.00 Jan. 18, 2008 Page 1437 of 1458
REJ09B0033-0300