SH7720 Datasheet, PDF (1179/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 33 User Break Controller (UBC)
33.2.5 Break Address Mask Register B (BAMRB)
BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address
specified by BARB.
Initial
Bit
Bit Name Value R/W Description
31 to 0 BAMB31 to All 0
BAMB0
R/W Break Address Mask B
Specifies bits masked in the break address of channel
B specified by BARB (BAB31 to BAB0).
0: Break address BABn of channel B is included in the
break condition
1: Break address BABn of channel B is masked and is
not included in the break condition
Note: n = 31 to 0
33.2.6 Break Data Register B (BDRB)
BDRB is a 32-bit readable/writable register. The control bits CDB1, CDB0, XYE, and XYS in the
break bus cycle register (BBRB) select one of the four data buses for break condition B.
Initial
Bit
Bit Name Value R/W Description
31 to 0 BDB31 to All 0
BDB0
R/W Break Data Bit B
Stores data which specifies a break condition in
channel B.
If the I bus is selected in BBRB, the break data on IDB
is set in BDB31 to BDB0.
If the L bus is selected in BBRB, the break data on LDB
is set in BDB31 to BDB0.
If the X memory is selected in BBRB, the break data in
bits 15 to 0 in XDB is set in BDB31 to BDB16. In this
case, the values in BDB15 to BDB0 are arbitrary.
If the Y memory is selected in BBRB, the break data in
bits 15 to 0 in YDB are set in BDB15 to BDB0. In this
case, the values in BDB31 to BDB16 are arbitrary.
Rev. 3.00 Jan. 18, 2008 Page 1117 of 1458
REJ09B0033-0300