SH7720 Datasheet, PDF (181/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
Table 3.18 Correspondence between DSP Instruction Operands and Registers
Register Sx
A0
Yes
A1
Yes
M0
M1
X0
Yes
X1
Yes
Y0
Y1
ALU Operations
Sy
Dz
Du
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Multiply Operations
Se
Sf
Dg
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
When writing parallel instructions, the field-B instruction is written first, followed by the field-A
instruction. A sample parallel processing program is shown in figure 3.6.
PADD A0, M0, A0
DCF PINC M1, A1
PCMP M1, M0
PMULS X0, Y0, M0
MOVX.W @R4+, X0
MOVX.W @R5+R8, X0
MOVX.W @R4, X1
MOVY.W @R6+, Y0
MOVY.W @R7+, Y1
[NOPY]
Figure 3.6 Sample Parallel Instruction Program
Square brackets mean that the contents can be omitted.
The no operation instructions NOPX and NOPY can be omitted. For details on the field B in DSP
data operation instructions, refer to section 3.6.4, DSP Operation Instructions.
The DSR register condition code bit (DC) is always updated on the basis of the result of an
unconditional ALU or shift operation instruction. Conditional instructions do not update the DC
bit. Multiply instructions, also, do not update the DC bit. DC bit updating is performed by means
of the CS[2:0] bits in the DSR register. The DC bit update rules are shown in table 3.19.
Rev. 3.00 Jan. 18, 2008 Page 119 of 1458
REJ09B0033-0300