SH7720 Datasheet, PDF (1470/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
Page Revision (See Manual for Details)
Section 11 Clock Pulse Generator 453
(CPG)
11.1 Features
Deleted
• Clocks for specific modules generated: In addition to
Iφ, Pφ, and Bφ, two other clocks, USBH/USBF clock
(Uφ), can be generated for specific modules. Uφ is a
clock input from an external pin.
Table 11.1 Pin Configuration
457 Amended
Note: To prevent device malfunction, the value of the
mode control pin is sampled only upon a power-
on reset.
11.3 Clock Operating Modes
458 Changed
Mode 0: …… The frequency of CKIO ranges from
24.00 to 66.67 MHz, because the input clock
frequency ranges from 24.00 to 66.67 MHz.
Section 11 Clock Pulse Generator 461
(CPG)
11.4.1 Frequency Control
Register (FRQCR)
Changed
…FRQCR is initialized by a power-on reset, but not
initialized by a power-on reset at the WDT overflow.
FRQCR retains its value in a manual reset and in
standby mode.
461 Deleted
Bit Bit Name Description
15 PLL2EN PLL2 Enable
PLL2EN specifies whether make the PLL
circuit 2 ON in clock operating mode 7.
When the PLL circuit 2 is necessary to
output the USBH/USBF clock, PLL2EN
makes the circuit ON. The PLL circuit 2 is
ON in non-clock operating mode 7
regardless of the PLL2EN setting.
0: PLL circuit 2 is OFF
1: PLL circuit 2 is ON
Rev. 3.00 Jan. 18, 2008 Page 1408 of 1458
REJ09B0033-0300