SH7720 Datasheet, PDF (377/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
Bit
10
9
8
7
6
5 to 2
1
0
Initial
Bit Name Value R/W Description
W3
1
R/W Number of Access Wait Cycles
W2
0
R/W Specify the number of wait cycles to be inserted in the first
W1
1
R/W ^{access cycle.}
W0
0
R/W ^{0000: 0 cycles}
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
WM
0
R/W External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the number
of access wait cycles is 0.
0: External wait is valid
1: External wait is ignored

All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
HW1
0
R/W Number of Delay Cycles from RD, WEn (BEn) negation to
HW0
0
R/W ^{Address, CSn negation}
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation. These bits
can be specified only in area 4.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 3.00 Jan. 18, 2008 Page 315 of 1458
REJ09B0033-0300