SH7720 Datasheet, PDF (747/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value
4
SYNCDL 0
3 to 0 
All 0
R/W
R/W
R
Description
Data Pin Bit Delay for SIOFSYNC Pin
Valid when the SIOFSYNC signal is output as
synchronous pulse. Only one-bit delay is valid for
transmission in slave mode.
0: No bit delay
1: 1-bit delay
Reserved
These bits are always read as 0. The write value should
always be 0.
Table 21.2 Operation in Each Transfer Mode
Transfer Mode Master/Slave SIOFSYNC
Bit Delay
Control Data Method*¹
Slave mode 1
Slave
Synchronous
pulse
SYNCDL bit
Slot position
Slave mode 2
Slave
Synchronous
pulse
Secondary FS
Master mode 1 Master
Synchronous
pulse
Slot position
Master mode 2 Master
L/R
No*²
Not supported
Notes: *1 The control data method is valid only when the FL bit is specified as 1xxx. (x: Don't
care.)
*2 Depending on the timing to start SYNC signal output in master mode 2, the SYNC
signal of the head frame in the high period can be extended to I bit. For details, see
section 21.5, Usage Notes.
Rev. 3.00 Jan. 18, 2008 Page 685 of 1458
REJ09B0033-0300