SH7720 Datasheet, PDF (1118/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
Initial
Bit
Bit Name Value R/W Description
2
SET2 0
R/W Sets DMA request signal assert condition.
1
SET1 0
R/W 000: Not output (Initial value)
0
SET0 0
R/W 001: FIFO remained data is 1/4 or less of FIFO capacity.
010: FIFO remained data is 1/2 or less of FIFO capacity.
011: FIFO remained data is 3/4 or less of FIFO capacity.
100: FIFO remained data is at least 1 byte.
101: FIFO remained data is 1/4 or more of FIFO capacity.
110: FIFO remained data is 1/2 or more of FIFO capacity.
111: FIFO remained data is 3/4 or more of FIFO capacity.
31.3.20 Interrupt Control Register 2 (INTCR2)
The INTCR2 enables or disables an interrupt.
Initial
Bit
Bit Name Value
7
INTRQ3E 0
6 to 1 
All 0
0
FRDYIE 0
R/W Description
R/W int_frdy_nb Interrupt Enable
0: Interrupt disabled
1: Interrupt enabled

Reserved
These bits are always read as 0. The write value should
always be 0.
R/W FIFO Preparation End Flag Enable
0: Disables FIFO preparation end flag set
1: Enables FIFO preparation end flag set
Rev. 3.00 Jan. 18, 2008 Page 1056 of 1458
REJ09B0033-0300