SH7720 Datasheet, PDF (1278/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 35 I/O Ports
35.18.2 Port V Data Register (PVDR)
PVDR is a register that stores data for pins PTV4 to PTV0. Bits PV4DT to PV0DT correspond to
pins PTV4 to PTV0. When the pin function is general output port, if the port is read, the value of
the corresponding PVDR bit is returned directly. When the function is general input port, if the
port is read, the corresponding pin level is read.
Initial
Bit Bit Name Value R/W Description
7 to 5 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
4
PV4DT 0
R/W Table 35.18 shows the function of PVDR.
3
PV3DT 0
R/W
2
PV2DT 0
R/W
1
PV1DT 0
R/W
0
PV0DT 0
R/W
Table 35.18 Port V Data Register (PVDR) Read/Write Operations
PVCR State
PVnMD1 PVnMD0 Pin State
Read
Write
0
0
Other function PVDR value Value is written to PVDR, but does not affect
pin state.
1
Output
PVDR value Write value is output from pin.
1
0
Input (Pull-up Pin state
Value is written to PVDR, but does not affect
MOS on)
pin state.
1
Input (Pull-up Pin state
Value is written to PVDR, but does not affect
MOS off)
pin state.
Note: n = 0 to 4
Rev. 3.00 Jan. 18, 2008 Page 1216 of 1458
REJ09B0033-0300