SH7720 Datasheet, PDF (1065/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 30 SIM Card Module (SIM)
Initial
Bit Bit Name Value R/W Description
2
SINV
0
R/W Smart Card Data Inversion
Specifies inversion of the data logic level. In combination with
the function of bit 3, used for transmission to or reception from
the inverse convention card. The SINV bit does not affect the
parity bit.
0: Transmits the SCTDR contents without change.
Stores received data in SCRDR without change.
1: Inverts the SCTDR contents and transmits it.
Inverts received data and stores it in SCRDR.
1
RST
0
R/W Smart Card Reset
Controls the output of the SIM_RST pin of the smart card
interface.
0: The SIM_RST pin of the smart card interface outputs low
level.
1: The SIM_RST pin of the smart card interface outputs high
level.
0
SMIF
1
R/W Smart Card Interface Mode Select
This bit is always read as 1. The write value should always be 1.
30.3.10 Serial Control 2 Register (SCSC2R)
SCSC2R is an 8-bit readable/writable register that enables or disables receive data full interrupt
(RXI) requests.
Initial
Bit Bit Name Value R/W Description
7
EIO
0
R/W Error Interrupt Only
When the EIO bit is 1, even if the RIE bit is set to 1, a receive
data full interrupt (RXI) request is not sent to the CPU. When the
DMAC is used with this setting, the CPU processes only ERI
requests.
Receive data full interrupt (RXI) requests are determined by the
RIE bit setting.
6 to 0 
All 0 R Reserved
These bits are always read as 0. The write value should always
be 0.
Rev. 3.00 Jan. 18, 2008 Page 1003 of 1458
REJ09B0033-0300