SH7720 Datasheet, PDF (168/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
3.4.2 DSP Data Addressing
Table 3.10 shows the relationship between the double data transfer instructions and single data
transfer instructions.
Table 3.10 Overview of Data Transfer Instructions
Address register
Index register
Addressing
Modulo addressing
Data bus
Data length
Bus conflict
Memory
Source register
Double Data Transfer
Instructions
MOVX.W
MOVY.W
Ax: R4, R5
Ay: R6, R7
Ix: R8, Iy: R9
Nop/Inc (+2)/index addition:
post-increment

Possible
XDB, YDB
16 bits (word)
No
X/Y data memory
Da: A0, A1
Destination register
Dx: X0/X1
Dy: Y0/Y1
Single Data Transfer Instructions
MOVS.W, MOVS.L
As: R2, R3, R4, R5
Is: R8
Nop/Inc (+2, +4)/index addition: post-
increment
Dec (–2, –4): pre-decrement
Not possible
LDB
16/32 bits (word/longword)
Yes
Entire memory space
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,
A0G, A1G
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,
A0G, A1G
Rev. 3.00 Jan. 18, 2008 Page 106 of 1458
REJ09B0033-0300