SH7720 Datasheet, PDF (476/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Descriptions
16
AL
0
R/W Acknowledge Level
Specifies whether the DACK signal output is high active
or low active.
This bit is valid only in CHCR_0 and CHCR_1. This bit
is always reserved and read as 0 in CHCR_2 to
CHCR_5. The write value should always be 0.
0: Low-active output of DACK
1: High-active output of DACK
15
DM1
0
R/W Destination Address Mode 1, 0
14
DM0
0
R/W Specify whether the DMA destination address is
incremented, decremented, or left fixed. (In single
address mode, the DM1 and DM0 bits are ignored
when data is transferred to an external device with
DACK.)
00: Fixed destination address (setting prohibited in 16-
byte transfer)
01: Destination address is incremented (+1 in byte-unit
transfer, +2 in word-unit transfer, +4 in longword-
unit transfer, +16 in 16-byte transfer)
10: Destination address is decremented (–1 in byte-unit
transfer, –2 in word-unit transfer, –4 in longword-
unit transfer; setting prohibited in 16-byte transfer)
11: Setting prohibited
13
SM1
0
R/W Source Address Mode 1, 0
12
SM0
0
R/W Specify whether the DMA source address is
incremented, decremented, or left fixed. (In single
address mode, SM1 and SM0 bits are ignored when
data is transferred from an external device with DACK.)
00: Fixed source address (setting prohibited in 16-byte
transfer)
01: Source address is incremented (+1 in byte-unit
transfer, +2 in word-unit transfer, +4 in longword-
unit transfer, +16 in 16-byte transfer)
10: Source address is decremented (–1 in byte-unit
transfer, –2 in word-unit transfer, –4 in longword-
unit transfer; setting prohibited in 16-byte transfer)
11: Setting prohibited
Rev. 3.00 Jan. 18, 2008 Page 414 of 1458
REJ09B0033-0300