SH7720 Datasheet, PDF (690/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
Initialization
Clear TE and RE bits in SCSCR to 0
Set TFRST and RFRST bits in
SCFCR to 1
1
Set CKE1 and CKE0 bits in SCSCR
(leaving TE and RE bits cleared to 0)
2
Set C/A bit in SCSMR to 1
Set CKS1 and CKS0 bits
3
Set value in SCBRR
4
Clear TFRST and RFRST bits to 0 5
Set transmit trigger number in TTRG1
and TTRG0 in SCFCR, write transmit
data exceeding transmit trigger ⁶
setting number, and clear TDFE
flag to 0 after reading 1 from it
Wait
1-bit interval elapsed?
Yes
End
7
No
1. Be sure to set the TFRST bit in
SCFCR to 1, to reset the FIFOs.
2. Set the clock selection in SCSCR.
Be sure to clear bits RIE, TIE, TE,
and RE to 0.
3. Set the clock source selection in
SCSMR.
4. Write a value corresponding to the
bit rate into SCBRR.
5. Clear the TFRST and RFRST bits in
SCFCR to 0.
6. Set the transmit trigger number, write
transmit data exceeding the transmit
trigger setting number, and clear the
TDFE flag to 0 after reading it.
7. Wait one bit interval.
Figure 18.13 Sample SCIF Initialization Flowchart (3)
(Simultaneous Transmission and Reception)
Rev. 3.00 Jan. 18, 2008 Page 628 of 1458
REJ09B0033-0300