SH7720 Datasheet, PDF (641/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Realtime Clock (RTC)
17.3.18 RTC Control Register 3 (RCR3)
When the ENB bit is set to 1, RCR3 performs a comparison with the RYRCNT. From among
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincide, an alarm flag of RCR1 is set to 1.
The ENB bit in RYRAR is initialized by a power-on reset. Remaining fields of RCR3 are not
initialized by a power-on reset or manual reset, or in standby mode.
Bit
7
6 to 0
Bit Name
ENB
Initial Value R/W
0
R/W

All 0
R
Description
When this bit is set to 1, comparison of the year
alarm register (RYRAR) and the year counter
(RYRCNT) is performed.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 3.00 Jan. 18, 2008 Page 579 of 1458
REJ09B0033-0300