SH7720 Datasheet, PDF (811/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 22 Analog Front End Interface (AFEIF)
(2) Ringing Interrupt Timing
As the figure 22.3 shows, the ringing signal from the line is transformed to rectangular wave and
then input to AFEIF. The interrupt is generated at the falling edge of input wave in AFEIF
module.
Ringing wave
Input wave
Interrupt occur
Figure 22.3 Ringing Interrupt Occurrence Timing
(3) Dial Pulse Interrupt Timing
Dial pulse interrupt is generated in the dial pulse transmit sequence when AFEIF reads 0H (end)
data from DPNQ register or all of 4 digits are output. Refer to section 22.4.3, DAA Interface about
dial pulse sequence.
(4) Interrupt Generator Circuit
Interrupt is generated as is shown in figure 22.4. That is, AFEIFI signal is generated by
performing OR operation on the four signals from ASTR1 in FIFO interrupt control and the two
signals from ASTR2 in DAA interrupt control, and then sent out to INTC as one interrupt signal.
ASTR1
Interrupt mask Interrupt factor
(FIFO control)
4
4
4
2
2
2
ASTR2
Interrupt mask Interrupt factor
(DAA control)
Figure 22.4 Interrupt Generator
AFEIFI
Rev. 3.00 Jan. 18, 2008 Page 749 of 1458
REJ09B0033-0300