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| SH7720 Datasheet, PDF (424/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series | |||
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Section 9 Bus State Controller (BSC)
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Tw
Td1
Td2
Td3
Td4
Tr
Trw
Tc1
Tc2
Tc3
Tc4
Tde
Tap
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.15 Burst Read Wait Specification Timing (Auto-Precharge)
Rev. 3.00 Jan. 18, 2008 Page 362 of 1458
REJ09B0033-0300
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